| Top-Metal Spiral Inductor | 0.5 to 20 nH | 1 to 20 GHz | 8 to 25 at the target frequency | Typically 10 to 40 GHz | 0.5 to 10 Ω | Approximately 5 to 80 mA | Planar metal spiral integrated in the upper interconnect layer of a silicon die; commonly 50 to 300 µm outer diameter | High-frequency performance and compact integration. Q is limited by metal and substrate loss; parasitic capacitance can reduce usable bandwidth. | RF matching networks, voltage-controlled oscillators, low-noise amplifiers, mixers, and impedance-transforming circuits |
| Differential Spiral Inductor | 0.5 to 15 nH differential inductance | 2 to 20 GHz | 7 to 22 at the target frequency | Typically 8 to 35 GHz | 0.8 to 12 Ω differential | Approximately 5 to 60 mA | Symmetrical two-terminal or center-tapped spiral structure with balanced layout on the silicon die | Provides good common-mode rejection and balanced RF operation. It generally occupies more area and may have lower Q than a carefully optimized single-ended structure. | Differential RF amplifiers, balanced filters, resonators, transceivers, and millimeter-wave front ends |
| Stacked or Multilayer Spiral Inductor | 1 to 30 nH | 1 to 15 GHz | 6 to 18 at the target frequency | Typically 6 to 25 GHz | 0.5 to 15 Ω | Approximately 5 to 100 mA | Vertically connected metal layers increase inductance per unit area; typical lateral size is 40 to 250 µm | Higher inductance density and reduced die area. Vertical interconnect loss, increased parasitic capacitance, and lower SRF require careful electromagnetic modeling. | RF integrated circuits, compact matching networks, resonant tanks, and frequency synthesizers |
| Thick-Metal Silicon Inductor | 1 to 50 nH | 0.5 to 10 GHz | 10 to 30 at the target frequency | Typically 5 to 20 GHz | 0.1 to 5 Ω | Approximately 20 to 300 mA | Wide or thick upper-metal conductors, often using an advanced redistribution or thick-metal process; typical size is 100 to 600 µm | Lower series resistance and higher current handling. It may require additional process steps and usually consumes more silicon area than a standard thin-metal spiral. | RF power amplifiers, supply isolation, integrated bias networks, and moderate-current impedance matching |
| Bond-Wire or Wire-Bond Integrated Inductor | 0.5 to 10 nH per wire configuration | 0.5 to 10 GHz | 5 to 20 at the target frequency | Typically 5 to 20 GHz | 0.05 to 2 Ω, excluding pad and lead losses | Approximately 50 to 500 mA, depending on wire diameter and thermal path | One or more package bond wires connected between die pads or package leads; electrical size is set by wire length and loop height | Very low added die area and useful current capacity. Inductance tolerance, parasitic coupling, assembly variation, and package dependence can be significant. | Package-level RF matching, power amplification, supply filtering, and customized high-frequency interconnects |
| Through-Silicon-Via Inductor | 1 to 20 nH | 0.5 to 8 GHz | 5 to 18 at the target frequency | Typically 3 to 15 GHz | 0.05 to 3 Ω | Approximately 50 to 500 mA | Vertical conductive vias arranged in a loop or coaxial-style structure through a silicon substrate or interposer | Enables vertical integration and short interconnects. TSV parasitic capacitance, substrate loss, thermal design, and fabrication cost must be controlled. | 3D integrated systems, silicon interposers, chiplet interconnects, RF modules, and vertically integrated power or signal networks |
| Deep-Trench or Embedded Silicon Inductor | 1 to 100 nH | 10 MHz to 5 GHz | 3 to 15 at the target frequency | Typically 1 to 10 GHz | 0.1 to 20 Ω | Approximately 10 to 300 mA | Conductive trench, buried metal, or three-dimensional silicon structure below the surface of the die | Improved area efficiency and potentially higher inductance. Substrate coupling, process complexity, limited Q, and model accuracy can be challenging. | On-chip power management, bias filtering, compact resonators, sensors, and specialized mixed-signal circuits |
| Low-Loss Silicon-on-Insulator Inductor | 0.5 to 30 nH | 1 to 40 GHz | 12 to 35 at the target frequency | Typically 15 to 60 GHz | 0.2 to 8 Ω | Approximately 5 to 100 mA | Planar or multilayer metal structure built on a high-resistivity or insulating silicon substrate | Reduced substrate loss, higher Q, and better isolation. Wafer cost, process availability, thermal behavior, and integration compatibility may be less favorable. | 5G and millimeter-wave circuits, high-performance oscillators, filters, phased arrays, and precision RF front ends |
| Integrated Power Inductor on Silicon Interposer | 10 nH to 1 µH | 1 MHz to 500 MHz | 2 to 15 at the target frequency | Typically 100 MHz to 3 GHz | 10 mΩ to 10 Ω | Approximately 0.1 to 5 A, depending on conductor thickness and thermal design | Large-area planar, multilayer, or magnetic-assisted structure on an interposer or package substrate; dimensions commonly range from 0.5 to several millimeters | Supports higher inductance and current than conventional RF on-die spirals. It requires more area and careful thermal, magnetic, and package co-design. | Point-of-load conversion, power delivery networks, voltage regulation modules, chiplet power systems, and energy-harvesting circuits |
| Magnetically Assisted Silicon-Integrated Inductor | 10 nH to 10 µH | 100 kHz to 200 MHz | 1 to 12 at the target frequency | Typically 10 MHz to 1 GHz | 20 mΩ to 20 Ω | Approximately 0.1 to 3 A | Silicon-compatible conductor combined with a deposited, laminated, or bonded magnetic material; footprint typically 0.5 to 10 mm | Higher inductance density and improved low-frequency energy storage. Core loss, magnetic saturation, temperature rise, material compatibility, and process reliability are key concerns. | Integrated DC-DC converters, power management ICs, energy storage, wireless power, and compact power modules |